This application claims the priority of Korean Patent Application No. 10-2005-0131459, filed on Dec. 28, 2005, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a row decoder for preventing leakage current from occurring even at a low supply voltage in a non-volatile memory device.
2. Description of the Related Art
A non-volatile semiconductor memory device such as a flash electrically erasable programmable read-only memory (EEPROM) device is usually used as a data storage device in a portable electronic system. Among various types of non-volatile semiconductor memory devices, NAND flash semiconductor memory devices having a NAND-type memory cell and NOR flash semiconductor memory devices having a NOR-type memory cell are commonly used.
In a flash memory device, a row decoder or a high-voltage switch has a direct current (DC) path when a supply voltage is low (e.g., “1.6V”), resulting in high power consumption. In the flash memory device, a boosted voltage higher than a supply voltage is internally used. The row decoder is a circuit which also needs the boosted voltage. Accordingly, when a DC path is formed from a boosted voltage node, power consumption increases.
FIG. 1 is a circuit diagram of a conventional row decoder 500. Referring to FIG. 1, when an enable signal EN is activated to a “high” level (1), a voltage of a gate 511 of a high-voltage positive-channel metal-oxide semiconductor (PMOS) transistor 541 transitions to a ground voltage level and the high-voltage PMOS transistor 541 is turned on. Then, a voltage of a node 512 is gradually increased by a negative-channel MOS (NMOS) depletion transistor 531 receiving the feedback of an output signal OUT. As a result, the voltage of the output signal OUT increases to the level of a boosted voltage VPP.
However, when the enable signal EN is deactivated, the voltage of a first node 511, an output node of an inverter 551, has a level of a supply voltage VCC and the output voltage of an inverter 552 has a ground voltage level (0 V). Accordingly, an NMOS transistor 521 and an NMOS depletion transistor 532 are turned on, and thus an electrical path is formed from an output node 513 to a ground voltage node (not shown) of the inverter 552. As a result, the voltage level of the output signal OUT decreases to 0 V. Assuming that the supply voltage VCC is about 1.6 V, when the threshold voltage of the NMOS depletion transistor 531 is about −2.5 V, the voltage of the node 512 is about 2.5 V. Accordingly, a voltage difference occurs between a source and a gate of the PMOS transistor 541 and the PMOS transistor is turned on. Then, as shown in FIG. 1, a DC path is formed between a boosted voltage node (VPP) and the ground voltage node, which causes an increase in power consumption.
As described above, in conventional decoders, a DC path is formed even when an enable signal is deactivated, and therefore, power consumption increases.